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ELECTRICAL CHARACTERISTICS
Unless otherwise specified: 0 ° C < T A < 70 ° C, 3.0V < V CC < 5.5V, C COMP = 22nF, C PDRV = C NDRV = 3.3nF, V FB = 1.25V, I SET = I SENSE = V CC , GND=0V
PARAMETER
MIN
TYP
MAX UNITS CONDITIONS
SOFT START, SHUTDOWN, UVLO: continued
Shutdown Threshold Voltage
Shutdown Input Pull-up Current
V CC Start Threshold
V CC Stop Threshold
V CC Hysteresis
0.2
2.69
2.59
-
0.3
5
2.79
2.69
100
0.4
2.89
2.79
-
V
μ A
V
V
mV
Measured at COMP Pin
COMP = 0.2V, Measured at COMP pin
GATE DRIVERS
PDRV Rise Time
PDRV Fall Time
NDRV Rise Time
PDRV Fall Time
PDRV to NDRV Non-Overlap Time
NDRV to PDRV Non-Overlap Time
-
-
-
-
40
40
40
40
80
50
110
110
110
110
ns
ns
ns
ns
ns
ns
V CC > 4.5V
V CC > 4.5V
V CC > 4.5V
V CC > 4.5V
V CC > 4.5V
V CC > 4.5V
PIN DESCRIPTION
PIN NO.
PIN NAME DESCRIPTION
1
2
3
4
5
6
7
8
V CC
GND
V FB
COMP
I SENSE
I SET
NDRV
PDRV
Positive input supply for the control circuitry and gate drivers. Properly bypass this pin
to GND with a low ESL/ESR ceramic capacitor.
Ground pin. Both power and control circuitry of the IC is referenced to this pin.
Feedback Voltage Pin. It is the inverting input of the Error Amplifier and serves as the
output voltage feedback point for the buck converter. The output voltage is sensed and
can be adjusted through an external resistor divider.
Output of the Error Amplifier. It is internally connected to the non-inverting input of the
PWM comparator. A lead-lag network is typically connected to the COMP pin to
compensate the feedback loop in order to optimize the dynamic performance of the
voltage mode control loop. Sleep mode can be invoked by pulling the COMP pin below
0.2V with an external open-drain or open-collector transistor. Supply current is reduced
to 25 μ A (typical) in shutdown. An internal 5 μ A pull-up ensures start-up.
Current Limit Sense pin. Connect this pin to the switching node at the junction between
the two external power MOSFET transistors. This pin monitors the voltage dropped
across the R DS(ON) of the high side P-channel MOSFET while it is conducting. When
this drop exceeds the sum of the voltage programmed through the I SET pin plus the
internal 160mV threshold, the overcurrent comparator sets the fault latch and termi-
nates the output pulses. The controller stops switching and goes through a hiccup
sequence. This prevents excessive power dissipation in the external power MOSFETs
during an overload condition. An internal delay circuit prevents that very short and mild
overload conditions, that could occur during a load transient, activate the current limit
circuit.
Current Limit Threshold pin. An external resistor connected between this pin and the
source of the high side P-channel MOSFET adds to the internal current limit threshold
of 160mV. If a current limit threshold in excess of 160mV is required, the external
programming resistor can properly be chosen based on the internal 30 μ A pull down
current available on the I SET pin. Both this 30 μ A current source and the 160mV built-in
current limit threshold have a positive temperature coefficient to provide first order
correction for the temperature coefficient of the external P-channel MOSFET’s R DS(ON) .
High current driver output for the low side MOSFET switch. It is always low if PDRV is
low or during a fault.
High current driver output for the high side MOSFET switch. It is always high if NDRV
is high or during a fault.
Date: 11/29/04
SP6121 Low Voltage, Synchronous Step Down PWM Controller
3
? Copyright 2004 Sipex Corporation
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